Freescale Semiconductor /MKL28T7_CORE1 /SCG /CSR

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Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)DIVSLOW0 (0000)DIVCORE0SCS

DIVSLOW=0000, DIVCORE=0000

Description

Clock Status Register

Fields

DIVSLOW

Slow Clock Divide Ratio

0 (0000): Divide-by-1

1 (0001): Divide-by-2

2 (0010): Divide-by-3

3 (0011): Divide-by-4

4 (0100): Divide-by-5

5 (0101): Divide-by-6

6 (0110): Divide-by-7

7 (0111): Divide-by-8

8 (1000): Divide-by-9

9 (1001): Divide-by-10

10 (1010): Divide-by-11

11 (1011): Divide-by-12

12 (1100): Divide-by-13

13 (1101): Divide-by-14

14 (1110): Divide-by-15

15 (1111): Divide-by-16

DIVCORE

Core Clock Divide Ratio

0 (0000): Divide-by-1

1 (0001): Divide-by-2

2 (0010): Divide-by-3

3 (0011): Divide-by-4

4 (0100): Divide-by-5

5 (0101): Divide-by-6

6 (0110): Divide-by-7

7 (0111): Divide-by-8

8 (1000): Divide-by-9

9 (1001): Divide-by-10

10 (1010): Divide-by-11

11 (1011): Divide-by-12

12 (1100): Divide-by-13

13 (1101): Divide-by-14

14 (1110): Divide-by-15

15 (1111): Divide-by-16

SCS

System Clock Source

1 (0001): System OSC

2 (0010): Slow IRC

3 (0011): Fast IRC

6 (0110): System PLL

Links

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